| CPC H10D 64/689 (2025.01) [H01L 21/02181 (2013.01); H01L 21/02192 (2013.01); H01L 21/28185 (2013.01); H10D 64/514 (2025.01); H10D 64/691 (2025.01); H10D 84/0144 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01); H10D 84/834 (2025.01); H10B 10/12 (2023.02)] | 20 Claims |
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1. A semiconductor device, comprising:
a first transistor comprising:
a first active region, and
a first gate dielectric layer over the first active region and comprising a first concentration of a dipole inducing material;
a second transistor comprising:
a second active region, and
a second gate dielectric layer over the second active region and comprising a second concentration of the dipole inducing material; and
a third transistor comprising:
a third active region, and
a third gate dielectric layer over the third active region and comprising a third concentration of the dipole inducing material,
wherein the first gate dielectric layer, the second gate dielectric layer and the third gate dielectric layer comprise same dimensions,
wherein the dipole inducing material comprises lanthanum, aluminum, or yttrium,
wherein the first concentration is greater than the second concentration and the second concentration is greater than the third concentration,
wherein the first transistor, the second transistor and the third transistor share a common functional metal gate stack that interfaces the first gate dielectric layer, the second gate dielectric layer and the third gate dielectric layer,
wherein the common functional metal gate stack is structurally and dimensionally uniform over the first active region, the second active region and the third active region.
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