| CPC H10D 64/118 (2025.01) [H01L 23/3171 (2013.01); H01L 23/3192 (2013.01); H10D 30/015 (2025.01); H10D 30/475 (2025.01); H10D 62/8503 (2025.01); H10D 64/01 (2025.01); H10D 64/111 (2025.01); H10D 64/411 (2025.01); H01L 23/481 (2013.01)] | 11 Claims |
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1. A method of fabricating a transistor device, the method comprising:
providing a semiconductor substrate;
forming a first dielectric layer on the semiconductor substrate;
forming ohmic contact structures on the semiconductor substrate;
forming a second dielectric layer on the first dielectric layer and the ohmic contact structures, the second dielectric layer directly on the ohmic contact structures;
forming a gate channel by etching a first opening in the first dielectric layer and a second opening in the second dielectric layer, wherein a surface of the semiconductor substrate is exposed through the first opening;
forming a third dielectric layer on the second dielectric layer and in the gate channel;
forming at least one photoresist layer over the semiconductor substrate;
forming at least one opening in the at least one photoresist layer by selectively removing portions of the at least one photoresist layer to expose portions of the third dielectric layer that are disposed in the gate channel;
selectively etching the exposed portions of the third dielectric layer to expose at least the surface of the semiconductor substrate; and
forming a gate structure in at least the gate channel and in contact with the surface of the semiconductor substrate.
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