US 12,477,782 B2
Thin film transistor, method of manufacturing the thin film transistor, and display apparatus including the thin film transistor
JeongSuk Yang, Paju-si (KR); KwangMin Jo, Paju-si (KR); and Sohyung Lee, Paju-si (KR)
Assigned to LG DISPLAY CO., LTD., Seoul (KR)
Filed by LG Display Co., Ltd., Seoul (KR)
Filed on May 23, 2024, as Appl. No. 18/672,820.
Application 18/672,820 is a division of application No. 17/029,889, filed on Sep. 23, 2020, granted, now 12,034,082.
Claims priority of application No. 10-2019-0117409 (KR), filed on Sep. 24, 2019; and application No. 10-2019-0179566 (KR), filed on Dec. 31, 2019.
Prior Publication US 2024/0313127 A1, Sep. 19, 2024
Int. Cl. H01L 29/786 (2006.01); H01L 27/12 (2006.01); H01L 29/66 (2006.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01); H10K 59/121 (2023.01); H10K 59/124 (2023.01)
CPC H10D 30/6757 (2025.01) [H10D 30/0321 (2025.01); H10D 30/6706 (2025.01); H10D 30/6715 (2025.01); H10D 30/6755 (2025.01); H10D 86/423 (2025.01); H10D 86/60 (2025.01); H10K 59/1213 (2023.02); H10K 59/124 (2023.02)] 13 Claims
OG exemplary drawing
 
1. A display apparatus comprising:
a first thin film transistor including a first active layer including polycrystalline silicon, a first gate electrode overlapping the first active layer with a first gate insulation layer therebetween, and a first source electrode and a first drain electrode each connected to the first active layer;
a first interlayer insulation layer disposed on the first gate electrode;
a second thin film transistor including a second active layer including an oxide semiconductor, a second gate electrode overlapping the second active layer with a second gate insulation layer therebetween, and a second source electrode and a second drain electrode each connected to the second active layer; and
a second interlayer insulation layer disposed on the first gate electrode, the second gate electrode, and the second gate insulation layer,
wherein the second gate insulation layer and the second interlayer insulation layer comprise a dopant for doping the second active layer,
wherein the second active layer comprises:
a second channel region overlapping the second gate electrode;
a second source region disposed at one side of the second channel region and connected to the second source electrode; and
a second drain region disposed at another side of the second channel region and connected to the second source electrode,
wherein the second source region comprises a first conductivity-providing part disposed at the one side of the second channel region and a first offset part disposed between the first conductivity-providing part and the one side of the second channel region,
wherein the second drain region comprises a second conductivity-providing part disposed at the other side of the second channel region and a second offset part disposed between the second conductivity-providing part and the other side of the second channel region,
wherein the first conductivity-providing part, the second conductivity-providing part, the first offset part, and the second offset part comprise the dopant,
wherein the first offset part has a concentration gradient of the dopant linearly increasing in a direction from the second channel region to the first conductivity-providing part, and
wherein the second offset part has a concentration gradient of the dopant linearly increasing in a direction from the second channel region to the second conductivity-providing part.