US 12,477,776 B2
Nanowire transistor with source and drain induced by electrical contacts with negative Schottky barrier height
Paul A. Clifton, Palo Alto, CA (US); Andreas Goebel, Mountain View, CA (US); and Walter A. Harrison, Palo Alto, CA (US)
Assigned to Acorn Semi, LLC, Palo Alto, CA (US)
Filed by Acorn Semi, LLC, Palo Alto, CA (US)
Filed on Jun. 21, 2024, as Appl. No. 18/750,751.
Application 16/202,507 is a division of application No. 15/816,231, filed on Nov. 17, 2017, granted, now 10,170,627, issued on Jan. 1, 2019.
Application 18/750,751 is a continuation of application No. 17/931,052, filed on Sep. 9, 2022, granted, now 12,034,078.
Application 17/931,052 is a continuation of application No. 17/091,959, filed on Nov. 6, 2020, granted, now 11,462,643, issued on Oct. 4, 2022.
Application 17/091,959 is a continuation of application No. 16/693,143, filed on Nov. 22, 2019, granted, now 10,833,199, issued on Nov. 10, 2020.
Application 16/693,143 is a continuation of application No. 16/202,507, filed on Nov. 28, 2018, granted, now 10,505,047, issued on Dec. 10, 2019.
Claims priority of provisional application 62/456,437, filed on Feb. 8, 2017.
Claims priority of provisional application 62/424,176, filed on Nov. 18, 2016.
Prior Publication US 2024/0347641 A1, Oct. 17, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10D 30/67 (2025.01); B82Y 10/00 (2011.01); H10D 30/43 (2025.01); H10D 30/62 (2025.01); H10D 62/10 (2025.01); H10D 62/13 (2025.01); H10D 64/23 (2025.01); H10D 64/64 (2025.01)
CPC H10D 30/6713 (2025.01) [B82Y 10/00 (2013.01); H10D 30/43 (2025.01); H10D 30/62 (2025.01); H10D 30/6211 (2025.01); H10D 30/6219 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01); H10D 62/151 (2025.01); H10D 64/251 (2025.01); H10D 64/647 (2025.01)] 38 Claims
OG exemplary drawing
 
1. A transistor, comprising:
a stack of nanosheets, each having a channel region of a first semiconductor material disposed longitudinally between and electrically coupled with a semiconductor source region and a semiconductor drain region, wherein the semiconductor source region is included in a source stack comprising a source conductor contacting the semiconductor source region and extending along at least a portion of the semiconductor source region, the source conductor comprising a degenerately doped n-type semiconductor having an offset in conduction band energy between the degenerately doped n-type semiconductor and the semiconductor source region such that a conduction band minimum in the degenerately doped n-type semiconductor is at a higher energy than a conduction band minimum in the semiconductor source region; and
a gate stack having a gate conductor and a gate insulator wrapping completely around each of the channel regions of the nanosheets.