| CPC H10D 30/6215 (2025.01) [H10D 30/0245 (2025.01); H10D 30/611 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01)] | 20 Claims |
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1. A method for forming a multi-gate semiconductor structure, comprising:
receiving a substrate comprising a fin structure, the fin structure comprising a plurality of first semiconductor layers and a plurality of second semiconductor layers arranged alternating with the plurality of first semiconductor layers;
disposing a sacrificial gate structure over a portion of the fin structure;
removing portions of the fin structure exposed through the sacrificial gate structure to form a recess in the substrate, wherein the first semiconductor layers and the second semiconductor layers are exposed through sidewalls of each recess;
forming an inner spacer coupled to each second semiconductor layer exposed through the sidewalls of the recess;
disposing a dielectric structure over the substrate;
removing a portion of the sacrificial gate structure to form a gate trench in the dielectric structure;
removing the plurality of second semiconductor layers exposed through the gate trench; and
performing a wet operation to trim a thickness of each of the plurality of first semiconductor layers and form a plurality of nanosheets in the gate trench.
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