US 12,477,770 B2
Group III-nitride high-electron mobility transistors with buried p-type layers and process for making the same
Saptharishi Sriram, Cary, NC (US); Thomas J. Smith, Raleigh, NC (US); Alexander Suvorov, Durham, NC (US); and Christer Hallin, Hillsborough, NC (US)
Assigned to Wolfspeed, Inc., Durham, NC (US)
Filed by Wolfspeed, Inc., Durham, NC (US)
Filed on Nov. 29, 2023, as Appl. No. 18/523,174.
Application 17/123,727 is a division of application No. 16/376,596, filed on Apr. 5, 2019, granted, now 10,892,356, issued on Jan. 12, 2021.
Application 18/523,174 is a continuation of application No. 17/123,727, filed on Dec. 16, 2020, granted, now 11,862,719.
Application 16/376,596 is a continuation in part of application No. 16/260,095, filed on Jan. 28, 2019, granted, now 10,840,334, issued on Nov. 17, 2020.
Application 16/260,095 is a continuation in part of application No. 15/424,209, filed on Feb. 3, 2017, granted, now 10,192,980, issued on Jan. 29, 2019.
Application 15/424,209 is a continuation in part of application No. 15/192,545, filed on Jun. 24, 2016, granted, now 11,430,882, issued on Aug. 30, 2022.
Prior Publication US 2024/0105829 A1, Mar. 28, 2024
Int. Cl. H01L 29/778 (2006.01); H01L 29/10 (2006.01); H01L 29/20 (2006.01); H01L 29/40 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H10D 30/01 (2025.01); H10D 30/47 (2025.01); H10D 62/17 (2025.01); H10D 62/85 (2025.01); H10D 64/00 (2025.01); H10D 64/23 (2025.01); H10D 64/27 (2025.01)
CPC H10D 30/475 (2025.01) [H10D 30/015 (2025.01); H10D 30/4732 (2025.01); H10D 30/4755 (2025.01); H10D 62/357 (2025.01); H10D 62/8503 (2025.01); H10D 64/111 (2025.01); H10D 64/251 (2025.01); H10D 64/411 (2025.01); H10D 62/343 (2025.01); H10D 64/256 (2025.01)] 38 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a substrate;
a group III-Nitride buffer layer on the substrate;
a group III-Nitride barrier layer on the group III-Nitride buffer layer, the group III-Nitride barrier layer comprising a higher bandgap than a bandgap of the group III-Nitride buffer layer;
a source electrically coupled to the group III-Nitride barrier layer;
a gate electrically coupled to the group III-Nitride barrier layer;
a drain electrically coupled to the group III-Nitride barrier layer; and
a p-region being at least one of the following: in the substrate or on the substrate;
wherein the source is electrically connected to the p-region;
wherein the p-region is below the group III-Nitride barrier layer and the p-region is structured and arranged to extend a limited length parallel to the group III-Nitride barrier layer;
wherein the p-region extends to a point before a proximal edge of the gate and the p-region is at most under only part of the gate; and
wherein the proximal edge of the gate is located on the group III-Nitride barrier layer and on a source side of the gate.