US 12,477,756 B2
Metal-insulator-metal structure and methods of fabrication thereof
Chih-Fan Huang, Kaohsiung (TW); Hung-Chao Kao, Taipei (TW); Yuan-Yang Hsiao, Taipei (TW); Tsung-Chieh Hsiao, Changhua County (TW); Hsiang-Ku Shen, Hsinchu (TW); Hui-Chi Chen, Hsinchu County (TW); Dian-Hau Chen, Hsinchu (TW); and Yen-Ming Chen, Hsin-Chu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Mar. 4, 2024, as Appl. No. 18/594,864.
Application 16/983,880 is a division of application No. 16/156,779, filed on Oct. 10, 2018, granted, now 10,734,474, issued on Aug. 4, 2020.
Application 18/594,864 is a continuation of application No. 17/750,729, filed on May 23, 2022, granted, now 11,923,405.
Application 17/750,729 is a continuation of application No. 16/983,880, filed on Aug. 3, 2020, granted, now 11,342,408, issued on May 24, 2022.
Claims priority of provisional application 62/711,711, filed on Jul. 30, 2018.
Prior Publication US 2024/0213305 A1, Jun. 27, 2024
Int. Cl. H10D 1/68 (2025.01); H01L 21/311 (2006.01); H01L 21/3213 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H10B 61/00 (2023.01)
CPC H10D 1/692 (2025.01) [H01L 21/31116 (2013.01); H01L 21/76804 (2013.01); H01L 21/76805 (2013.01); H01L 23/5226 (2013.01); H10B 61/10 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a multi-layer interconnect structure disposed over a substrate;
a dielectric layer disposed over the multi-layer interconnect structure; and
a metal-insulator-metal (MIM) capacitor disposed over the dielectric layer, wherein the MIM capacitor includes:
a bottom electrode disposed on a top surface of the dielectric layer, wherein the bottom electrode has a slanted sidewall with respect to the top surface of the dielectric layer,
a top electrode disposed above the bottom electrode, wherein the top electrode has a vertical sidewall with respect to the top surface of the dielectric layer,
an insulating layer interposed between the bottom electrode and the top electrode, wherein the insulating layer covers the slanted sidewall of the bottom electrode, and
a first via electrically coupled to the top electrode and positioned directly above the top electrode.