| CPC H10B 43/30 (2023.02) [H10D 30/0413 (2025.01)] | 15 Claims |
|
1. A manufacturing method for a nonvolatile charge-trapping memory apparatus, the manufacturing method comprising steps of:
(A) forming a pad oxide layer on a surface of a semiconductor substrate, and forming plural isolation structures in the semiconductor substrate, wherein through the plural isolation structure, the semiconductor substrate is divided into a memory device area and a logic device area, and the logic device area is divided into an input/output device area and a core device area;
(B) forming a first photoresist layer to cover the logic device area, and forming a first first-type well region under the surface of the semiconductor substrate and in the memory device area;
(C) removing the first photoresist layer and at least a portion of the pad oxide layer, and forming a stack layer in the logic device area and the memory device area, wherein the stack layer comprises a bottom oxide layer, a trapping layer, a blocking layer and a protecting layer;
(D) forming a second photoresist layer to cover a portion of the stack layer in the memory device area, and removing portions of the protecting layer, the blocking layer and the trapping layer that are not covered by the second photoresist layer;
(E) removing the second photoresist layer, and forming a third photoresist layer to cover the memory device area;
(F) forming a second first-type well region, a first second-type well region and a first deep first-type well region under the surface of the semiconductor substrate and in the core device area, and forming a third first-type well region, a second second-type well region and a second deep first-type well region under the surface of the semiconductor substrate and in the input/output device area, wherein the first second-type well region is formed in the first deep first-type well region, and the second second-type well region is formed in the second deep first-type well region;
(G) removing the third photoresist layer, and removing a portion of the bottom oxide layer that is not covered by the protecting layer;
(H) removing the protecting layer of the stack layer, forming an input/output gate oxide layer on the surface of the semiconductor substrate and in the memory device area, forming the input/output gate oxide layer on the surface of the semiconductor substrate and in the input/output device area, and forming a core gate oxide layer on the surface of the semiconductor substrate and in the core device area;
(I) forming a gate layer to cover the memory device area and the logic device area; and
(J) forming plural gate structures, and forming plural doped regions,
wherein a first gate structure of the plural gate structures is formed over the first first-type well region, a first second-type doped region of the plural doped regions is formed in the first first-type well region and located beside a first side of the first gate structure, and a second second-type doped region of the plural doped regions is formed in the first first-type well region and located beside a second side of the first gate structure, wherein a second gate structure of the plural gate structures is formed over the first first-type well region, the second-type doped region is further located beside a first side of the second gate structure, and a third second-type doped region of the plural doped regions is formed in the first first-type well region and located beside a second side of the second gate structure,
wherein a third gate structure of the gate structures is formed over the second first-type well region, a fourth second-type doped region of the plural doped regions is formed in the second first-type well region and located beside a first side of the third gate structure, and a fifth second-type doped region of the plural doped regions is formed in the second first-type well region and located beside a second side of the third gate structure, wherein a fourth gate structure of the plural gate structures is formed over the first second-type well region, a first first-type doped region of the plural doped regions is formed in the first second-type well region and located beside a first side of the fourth gate structure, and a second first-type doped region of the plural doped regions is formed in the first second-type well region and located beside a second side of the fourth gate structure,
wherein a fifth gate structure of the plural gate structures is formed over the third first-type well region, a sixth second-type doped region of the plural doped regions is formed in the third first-type well region and located beside a first side of the fifth gate structure, and a seventh second-type doped region of the plural doped regions is formed in the third first-type well region and located beside a second side of the fifth gate structure, wherein a sixth gate structure of the plural gate structures is formed over the second second-type well region, a third first-type doped region of the plural doped regions is formed in the second second-type well region and located beside a first side of the sixth gate structure, and a fourth first-type doped region of the plural doped regions is formed in the second second-type well region and located beside a second side of the sixth gate structure.
|