| CPC H10B 43/27 (2023.02) [H10B 41/27 (2023.02); H10B 63/34 (2023.02); H10B 63/845 (2023.02)] | 8 Claims |
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1. A method of manufacturing a semiconductor device, comprising:
forming a stacked body;
forming a first hole configured to pass through the stacked body;
sequentially forming a memory layer, a preliminary channel layer, and a preliminary interposed layer in the first hole;
separating the preliminary interposed layer into a plurality of interposed layers by etching the preliminary interposed layer;
separating the preliminary channel layer into a plurality of channel layers; and
forming a filling layer coupled to the interposed layers and the channel layers,
an entirety of an inside wall of each of the plurality of channel layers is in contact with each of the plurality of interposed layers.
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