US 12,477,727 B2
Semiconductor memory device having a symmetric active area layout structure
Hung-Hsun Shuai, Tainan (TW); Yu-Jen Yeh, Taichung (TW); and Chih-Jung Chen, Hsinchu County (TW)
Assigned to UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed by UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed on Dec. 30, 2021, as Appl. No. 17/565,484.
Claims priority of application No. 202111451826.6 (CN), filed on Dec. 1, 2021.
Prior Publication US 2023/0171958 A1, Jun. 1, 2023
Int. Cl. H10B 41/40 (2023.01); G11C 16/24 (2006.01); G11C 16/28 (2006.01)
CPC H10B 41/40 (2023.02) [G11C 16/24 (2013.01); G11C 16/28 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A semiconductor memory device, comprising:
a substrate;
a plurality of device lines comprising a select gate (SG) line, a control gate (CG) line, an erase gate (EG) line, and a source line elongated in parallel along a first direction, wherein the CG line is disposed between the EG line and the SG line, and the source line underlies the EG line in the substrate, wherein the plurality of device lines defines a plurality of memory cells and at least one strap cell between the plurality of memory cells spaced along lengths of the device lines;
a plurality of bit line (BL) contacts electrically connected to a plurality of drain doped regions of the plurality of memory cells respectively, wherein the plurality of drain doped regions is adjacent to the SG line; and
at least one source line contact electrically connected to a diffusion region of the strap cell under the SG line, wherein the at least one source line contact is aligned with the plurality of BL contacts in the first direction, wherein the at least one strap cell comprises a dummy floating gate under the CG line, and an always-on floating gate channel directly under the dummy floating gate.