| CPC H10B 41/35 (2023.02) [H10B 12/00 (2023.02); H10B 41/10 (2023.02); H10B 41/60 (2023.02); H10B 41/70 (2023.02)] | 20 Claims |
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1. A memory device, comprising:
a first memory cell, including:
a first transistor;
a second transistor; and
a first capacitor coupled to the second transistor;
a second memory cell, including:
a third transistor;
a fourth transistor; and
a second capacitor coupled to the fourth transistor;
a third memory cell, including:
a fifth transistor;
a sixth transistor; and
a third capacitor coupled to the sixth transistor; and
a fourth memory cell, including:
a seventh transistor;
an eighth transistor; and
a fourth capacitor coupled to the eighth transistor;
wherein an electrode of the first capacitor, an electrode of the second capacitor, an electrode of the third capacitor, and an electrode of the fourth capacitor are electrically connected to a conductor disposed over an active region in a first well region,
wherein the first capacitor, the second capacitor, the third capacitor and the fourth capacitor overlap the active region and the first well region having the same conductivity type from a top view, and the first and second transistors are separated from the first well region.
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