| CPC H10B 12/30 (2023.02) [H10B 12/03 (2023.02); H10B 12/482 (2023.02); H10B 12/488 (2023.02); H10D 62/115 (2025.01)] | 10 Claims |
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1. A semiconductor device comprising:
a plurality of active layers vertically stacked in a first direction, and horizontally extended in a second direction perpendicular to the first direction;
a plurality of bit lines connected to first ends of the active layers, respectively, and horizontally extended in a third direction;
line-shape air gaps disposed between the bit lines;
a plurality of capacitors connected to second ends of the active layers, respectively;
a word line and a back gate facing each other with each of the active layers interposed therebetween, the word line and the back gate are vertically extended in the first direction,
a capping layer capping the line-shape air gaps,
a liner capping layer formed between the capping layer and the bit lines,
wherein the back gate has a length greater than that of the word line in the second direction,
wherein the word line and the back gate are applied with different voltages, and
wherein the line-shape air gaps are positioned between the capping layer and the liner capping layer.
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