US 12,477,717 B2
Semiconductor structure and manufacturing method thereof
Daohuan Feng, Hefei (CN); and Xiaojie Li, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Jul. 28, 2022, as Appl. No. 17/815,633.
Claims priority of application No. 202210633586.X (CN), filed on Jun. 6, 2022.
Prior Publication US 2023/0397399 A1, Dec. 7, 2023
Int. Cl. H10B 12/00 (2023.01)
CPC H10B 12/30 (2023.02) [H10B 12/03 (2023.02); H10B 12/05 (2023.02)] 14 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor structure, comprising:
providing a base;
forming active pillars and a bit line that extends along a first direction, wherein the bit line is located on a surface of the base, the active pillars are arranged at intervals along a direction perpendicular to the surface of the base, the active pillar comprises a source region, a channel region, a drain region, and a support region, and the bit line is connected to one of the source region and the drain region of the active pillar;
forming a word line extending along a second direction, wherein the word line is located between adjacent active pillars and surrounds the channel region of the active pillar; and
forming a plurality of memory structures, wherein the memory structures are vertically stacked on the base, the memory structure is connected to the other one of the source region and the drain region of the active pillar, the memory structure surrounds the support region of the active pillar, and the memory structures comprise a first electrode plate, a first dielectric layer, and a second electrode plate that are sequentially stacked on surfaces of the support regions of the active pillars; and forming the memory structures comprises:
providing an isolation layer between the word line and the memory structures, and forming a first conductive layer, a dielectric film, and a second conductive layer that are continuously and sequentially stacked on a side surface of the isolation layer and a surface of the active pillar; and
etching to remove a part of the first conductive layer located on the side surface of the isolation layer, to expose a side surface of the dielectric film, and taking a remaining part of the first conductive layer as the first electrode plate, a remaining part of the dielectric film as the first dielectric layer, and the second conductive layer as the second electrode plate;
wherein during the etching to remove a part of the first conductive layer located on the side surface of the isolation layer, a thickness of the dielectric film is reduced along an arrangement direction of the source region and the drain region of the active pillar.