US 12,477,712 B2
Memory structure and method for manufacturing the same
Hung-Ju Chou, Taipei (TW); and Yuan-Ching Peng, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on May 18, 2022, as Appl. No. 17/747,064.
Prior Publication US 2023/0380130 A1, Nov. 23, 2023
Int. Cl. H10B 10/00 (2023.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01)
CPC H10B 10/125 (2023.02) [H10D 30/6713 (2025.01); H10D 30/6729 (2025.01); H10D 30/6757 (2025.01); H10D 62/118 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A memory structure comprising:
a first pull-up (PU) transistor and a first pull-down (PD) transistor sharing a first gate structure extending in a first direction;
a second PU transistor and a second PD transistor sharing a second gate structure extending in the first direction; and
an active area shared by the first PD transistor and the second PD transistor, wherein
the first gate structure and the second gate structure are separated in a second direction, wherein the second direction is perpendicular to the first direction;
the first gate structure has a first PU portion that corresponds with the first PU transistor and a first PD portion that corresponds with the first PD transistor;
the second gate structure has a second PU portion that corresponds with the second PU transistor and a second PD portion that corresponds with the second PD transistor; and
the first PU portion and the second PU portion each has a first dimension in the second direction, and the first PD portion and the second PD portion each has a second dimension in the second direction, wherein the first dimension is greater than the second dimension,
wherein a distance between the first PD portion and the second PD portion in the second direction is greater than a distance between the first PU portion and the second PU portion in the second direction.