US 12,477,649 B2
Impedance tuning of microstrip traces
Sandor Farkas, Round Rock, TX (US); and Bhyrav Mutnury, Austin, TX (US)
Assigned to Dell Products L.P., Round Rock, TX (US)
Filed by DELL PRODUCTS L.P., Round Rock, TX (US)
Filed on Jul. 12, 2023, as Appl. No. 18/351,251.
Prior Publication US 2025/0024589 A1, Jan. 16, 2025
Int. Cl. H05K 1/02 (2006.01); H01P 3/08 (2006.01); H05K 1/11 (2006.01)
CPC H05K 1/0251 (2013.01) [H01P 3/08 (2013.01); H05K 1/0298 (2013.01); H05K 1/115 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A printed circuit board comprising:
a first connection pad coupled to a first portion of a microstrip trace;
a second connection pad coupled to a second portion of the microstrip trace;
the microstrip trace having a first impedance along the first portion and a second impedance along the second portion; and
a conductive plane on a top surface of the microstrip trace, wherein the conductive plane includes a plurality of cutouts to reduce impedance mismatch between the first impedance and the second impedance.