US 12,477,398 B2
Method and system for transmitting in-band cross-chip triggers to maintain high-speed interconnect
Adithya Hrudhayan Krishnamurthy, Sunnyvale, CA (US); and Ish Chadha, San Jose, CA (US)
Assigned to NVIDIA Corporation, Santa Clara, CA (US)
Filed by NVIDIA Corporation, Santa Clara, CA (US)
Filed on Oct. 18, 2022, as Appl. No. 17/968,210.
Claims priority of provisional application 63/294,041, filed on Dec. 27, 2021.
Prior Publication US 2023/0209405 A1, Jun. 29, 2023
Int. Cl. H04W 28/08 (2023.01); H04W 28/16 (2009.01); H04W 72/23 (2023.01)
CPC H04W 28/0967 (2020.05) [H04W 28/16 (2013.01); H04W 72/23 (2023.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a link comprising one or more data paths;
a device coupled with the link and comprising a data link (DL) transmitter and a buffer, the device to:
write, in response to an indication, one or more bits corresponding to an operation to a first portion of a data frame, the data frame comprising a second portion comprising data;
transmit the first portion and the second portion of the data frame via the one or more data paths in response to writing the one or more bits corresponding to the operation; and
store the data frame in the buffer in response to writing the one or more bits corresponding to the operation; and
a second device coupled to the link and comprising a second buffer, the second device to:
receive the data frame via the one or more data paths;
decode the data frame in response to receiving the data frame;
determine that the one or more bits in the first portion correspond to the operation; and
store the data frame in the second buffer in response to determining the one or more bits correspond to the operation.