| CPC H04N 25/78 (2023.01) [H04N 25/57 (2023.01); H04N 25/63 (2023.01)] | 23 Claims |

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1. A pixel processor comprising:
an input to receive signed digital pixel data corresponding to a plurality of pixels of a pixel array, the signed digital pixel data comprising a plurality of pixel-read values over a signed range, the plurality of pixel-read values comprising a plurality of negative pixel-read values over a negative sub-range of the signed range and a plurality of positive pixel-read values over a positive sub-range of the signed range;
a processor configured to generate unsigned digital pixel data over an unsigned range based on the signed digital pixel data, the unsigned digital pixel data comprising a first plurality of unsigned digital pixel values over a first sub-range of the unsigned range and a second plurality of unsigned digital pixel values over a second sub-range of the unsigned range, wherein the first plurality of unsigned digital pixel values is based on a black level scaling factor applied to the plurality of negative pixel-read values, the black level scaling factor is less than 1, wherein the second plurality of unsigned digital pixel values is based on the plurality of positive pixel-read values; and
an output to output processed pixel data based on the unsigned digital pixel data.
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