| CPC H04N 19/44 (2014.11) [H04N 19/105 (2014.11); H04N 19/172 (2014.11); H04N 19/423 (2014.11)] | 5 Claims |

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1. An encoder comprising:
circuitry; and
memory coupled to the circuitry, wherein
in operation, the circuitry:
stores a first flag into a sequence parameter set, the first flag indicating whether or not hypothetical reference decoder (HRD) parameters related to a decoding unit are present;
stores a second flag into a buffering period supplemental enhancement information (SEI) message, the second flag indicating whether or not the HRD parameters related to the decoding unit are present, a value of the second flag being equal to a value of the first flag; and
switches whether or not to store a first parameter included in the HRD parameters into the buffering period SEI message according to the second flag,
the buffering period SEI message does not include information for identifying the sequence parameter set, and
in a picture timing SEI message, the second flag is referred to and the first flag is not referred to.
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