US 12,476,941 B2
Load balancing secure network traffic
Pankaj Bhagra, Fremont, CA (US); Aniket Ghule, San Jose, CA (US); Srinivasan Komandoor Santhanam, Sunnyvale, CA (US); Arivu Mani Ramasamy, San Jose, CA (US); and Prashant Murlidhar Dave, Fremont, CA (US)
Assigned to Palo Alto Networks, Inc., Santa Clara, CA (US)
Filed by Palo Alto Networks, Inc., Santa Clara, CA (US)
Filed on Jul. 27, 2023, as Appl. No. 18/227,159.
Prior Publication US 2025/0039151 A1, Jan. 30, 2025
Int. Cl. H04L 9/40 (2022.01); H04L 12/46 (2006.01); H04L 43/0882 (2022.01); H04L 47/125 (2022.01); H04L 61/2546 (2022.01)
CPC H04L 63/029 (2013.01) [H04L 12/4633 (2013.01); H04L 43/0882 (2013.01); H04L 47/125 (2013.01); H04L 61/2546 (2013.01); H04L 63/1425 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A system, comprising:
a processor configured to:
monitor network traffic for one branch of a plurality of branches for an enterprise network; and
split the network traffic of the one branch into a plurality of network segments based on a determination that the network traffic exceeds traffic capacity of at least one security processing node (SPN) of a plurality of SPNs using a network load balancer (NLB) in communication with a plurality of Network Processing Nodes (NPNs), wherein the one monitored branch is distributed to the plurality of SPNs via a plurality of tunnels, wherein the splitting of the network traffic of the one branch into the plurality of network segments comprises to:
determine that the network traffic of the one branch exceeds the traffic capacity of the at least one SPN, wherein the network traffic of the one branch is associated with at least one prefix; and
in response to the determination that the network traffic of the one branch exceeds the traffic capacity of the at least one SPN, split the at least one prefix into a plurality of smaller prefixes, wherein the at least one prefix is broken into a first non-overlapping portion and a second non-overlapping portion; and
a memory coupled to the processor and configured to provide the processor with instructions.