US 12,476,921 B2
Server delay control device, server delay control method, and program
Kei Fujimoto, Musashino (JP); and Masashi Kaneko, Musashino (JP)
Assigned to NTT, Inc., Tokyo (JP)
Appl. No. 18/264,991
Filed by NTT, Inc., Tokyo (JP)
PCT Filed Feb. 10, 2021, PCT No. PCT/JP2021/005002
§ 371(c)(1), (2) Date Aug. 10, 2023,
PCT Pub. No. WO2022/172366, PCT Pub. Date Aug. 18, 2022.
Prior Publication US 2024/0129255 A1, Apr. 18, 2024
Int. Cl. H04L 47/56 (2022.01); H04L 43/103 (2022.01)
CPC H04L 47/568 (2013.01) [H04L 43/103 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A server delay control device for performing, on a server, packet transfer from an interface part of a computer comprising one or more hardware processors, the server comprising an OS and implemented using one or more of the one or more hardware processors, the OS comprising: a kernel in which the server delay control device is deployed; a ring buffer managed by the kernel, in a memory space in which the server deploys the OS; and a poll list in which information on a net device is registered, the information on the net device being indicative of which device a hardware interrupt from an interface part comes from, the server delay control device implemented using one or more of the one or more hardware processors, configured to receive a timer interrupt at predetermined specified intervals, and comprising:
a packet arrival monitoring part configured to configure the timer interrupt as a hardware interrupt and check the presence or absence of a packet in the poll list upon being triggered by the timer interrupt to monitor the poll list; and
a packet dequeuer configured to, when a packet has arrived, reference the packet held in the ring buffer, and perform dequeuing to remove a corresponding queue entry from the ring buffer.