US 12,476,784 B2
System and method of clock and data recovery
Michael Chung Wang, Southlake, TX (US); Neal Hays, Cupertino, CA (US); and Amir Amirkhany, Sunnyvale, CA (US)
Assigned to Samsung Electronics Co., Ltd., Yongin-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Oct. 4, 2023, as Appl. No. 18/481,226.
Claims priority of provisional application 63/454,596, filed on Mar. 24, 2023.
Prior Publication US 2024/0322994 A1, Sep. 26, 2024
Int. Cl. H04L 7/033 (2006.01); H03L 7/08 (2006.01); H03L 7/099 (2006.01)
CPC H04L 7/033 (2013.01) [H03L 7/0807 (2013.01); H03L 7/099 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
setting a bias signal source to a first bias value, the bias signal source being connected to an input of a voltage-controlled oscillator of a clock and data recovery circuit;
determining that a locked signal of a frequency feedback signal source equals or exceeds a first feedback value;
determining that the first feedback value does not meet a termination criterion;
setting the bias signal source to a second bias value, different from the first bias value;
determining that the locked signal of the frequency feedback signal source equals or exceeds a second feedback value;
determining that the second feedback value meets the termination criterion; and
based on determining that the second feedback value meets the termination criterion, setting an operating value of the bias signal source to the second bias value for the voltage-controlled oscillator of the clock and data recovery circuit.