| CPC H04L 7/0033 (2013.01) [H04L 7/033 (2013.01)] | 19 Claims |

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1. A network node synchronization system comprising:
a first node comprising
a first host card comprising a first host time of day (TOD) counter and a first embedded Pulse Per Second (ePPS) counter,
a first digital signal processor (DSP) comprising a first DSP counter, wherein the first DSP is a coherent DSP; and
a first optical communication device comprising a first DSP communication channel, wherein the first DSP communication channel transports DSP frames, wherein the first ePPS counter is in communication with both the first host TOD counter and the first DSP counter, wherein a phase of the first ePPS counter is locked with a phase of the first DSP counter using a phase locked loop (PLL).
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