| CPC H04L 1/0041 (2013.01) [H03M 13/1148 (2013.01); H03M 13/116 (2013.01); H03M 13/616 (2013.01); H03M 13/6306 (2013.01); H03M 13/6362 (2013.01); H03M 13/6516 (2013.01); H03M 13/6561 (2013.01); H04L 1/0045 (2013.01); H04L 1/0057 (2013.01); H04L 1/0069 (2013.01); H04L 1/1812 (2013.01); H04L 1/1819 (2013.01); H04L 1/1841 (2013.01); H04L 1/1864 (2013.01)] | 24 Claims |

|
1. An apparatus for wireless communications, comprising:
at least one processor coupled with a memory and comprising:
encoder circuitry configured to encode a set of information bits using a systematic code to generate an encoded bit stream with information bits and parity bits, wherein the systematic code comprises a lifted low-density parity-check (LDPC) code;
puncturing circuitry configured to puncture one or more information bits in the encoded bit stream according to a puncturing pattern; and
bit ordering circuitry configured to re-order bits in the encoded bit stream by interleaving the information bits with the parity bits to distribute the information bits and the parity bits in the encoded bit stream such that an equal number of check nodes, in the lifted LDPC code, having a single edge connected to a punctured information bit are included in transmissions associated with different redundancy versions (RVs); and
a transmitter configured to transmit the re-ordered bits in accordance with a radio technology across a wireless channel via one or more antenna elements situated proximate the transmitter.
|