	US 12,476,727 B2
	Method for disseminating scaling information and application thereof in VLSI implementation of fixed-point FFT
Xinzhe Liu, Shanghai (CN); Raees Kizhakkumkara Muhamad, Uccle (BE); Dessislava Nikolova, Borsbeek (BE); Yajun Ha, Shanghai (CN); Francky Catthoor, Temse (BE); Fupeng Chen, Shanghai (CN); Peter Schelkens, Willebroek (BE); and David Blinder, Antwerp (BE)
Assigned to Imec vzw, Leuven (BE); and ShanghaiTech University, Shanghai (CN)
Filed by IMEC VZW, Leuven (BE); and ShanghaiTech University, Shanghai (CN)
Filed on Oct. 26, 2022, as Appl. No. 18/049,932.
Claims priority of application No. 202111460635.6 (CN), filed on Dec. 2, 2021.
Prior Publication US 2023/0179315 A1, Jun. 8, 2023
Int. Cl. H04J 11/00 (2006.01)

CPC H04J 11/00 (2013.01)

12 Claims

7. A system, wherein the system simultaneously comprises a linear decomposable transformation process and an inverse process of the linear decomposable transformation process, wherein the inverse process of the linear decomposable transformation process is defined, in time or space, as an inverse linear decomposable transformation process, wherein the linear decomposable transformation process is separated from the inverse linear decomposable transformation process, wherein the linear decomposable transformation process or the inverse linear decomposable transformation process is able to be performed first and is defined as a linear decomposable transformation I, wherein the other remaining process is performed subsequently and is defined as a linear decomposable transformation II, wherein scaling information in the system is configured to be disseminated by a method, wherein the method is used for a bit width-optimized and energy-saving hardware implementation of linear decomposable transformation in digital signal processing (DSP), and wherein the method comprises:

in a system design stage:

negating an operation at each stage of the linear decomposable transformation II as an operation at a corresponding stage of the linear decomposable transformation I;

designing a bit width for each stage of the linear decomposable transformation II;

inserting a scaling information collection module and a scaling decision-making module in the linear decomposable transformation I; and

inserting a multiplexer in the linear decomposable transformation II; and

in a system run stage:

while running the linear decomposable transformation I:

collecting and calculating, by the scaling information collection module, a bit width and saturation cost that is required for each stage of the linear decomposable transformation II; and

determining, by the scaling decision-making module based on the bit width and saturation cost required for each stage, whether scaling is required to obtain a best scaling strategy, wherein determining whether scaling is required to obtain the best scaling strategy comprises:

in response to the bit width required at the current stage being smaller than a pre-designed bit width, determining, by the scaling decision-making module, that scaling is not required at the current stage; and

in response to the bit width required at the current stage being larger than the pre-designed bit width:

determining whether the saturation cost is greater than a fixed value hyperparameter n, wherein the fixed value hyperparameter n comprises a quantization error;

in response to the saturation cost being less than the fixed value hyperparameter n, determining, by the scaling decision-making module, that scaling is not required at the current stage; and

in response to the saturation cost being greater than the fixed value hyperparameter n, determining, by the scaling decision-making module, that scaling is required at the current stage; and

performing, by the multiplexer at each stage when the linear decomposable transformation II runs, a scaling decision, wherein the scaling decision was output by the scaling decision-making module.