US 12,476,648 B2
Noise shaping successive-approximation register (SAR) analog-to-digital converter (ADC)
Masashi Kijima, Aichi (JP); and Rajiv Singh, Bothell, WA (US)
Assigned to Cypress Semiconductor Corporation, San Jose, CA (US)
Filed by Cypress Semiconductor Corporation, San Jose, CA (US)
Filed on Jul. 25, 2023, as Appl. No. 18/358,681.
Prior Publication US 2025/0038757 A1, Jan. 30, 2025
Int. Cl. H03M 1/06 (2006.01); H03M 1/08 (2006.01)
CPC H03M 1/08 (2013.01) 18 Claims
OG exemplary drawing
 
1. A successive-approximation register (SAR) analog-to-digital converter (ADC) (SAR ADC) comprising:
a noise-shaping (NS) filter;
a comparator comprising a first input path coupled to receive a signal and a second input path coupled to the NS filter, wherein the second input path comprises:
a first transistor pair comprising a first transistor and a second transistor;
a first capacitive element coupled between a gate of the first transistor and a drain of the second transistor; and
a second capacitive element coupled between a gate of the second transistor and a drain of the first transistor.