US 12,476,643 B2
Phase lock loop reference loss detection
Shailesh Ganapat Ghotgalkar, Bangalore (IN); Wei Fu, Plano, TX (US); and Venkatseema Das, Bangalore (IN)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Apr. 17, 2024, as Appl. No. 18/638,065.
Application 18/638,065 is a continuation of application No. 17/550,123, filed on Dec. 14, 2021, granted, now 11,990,914.
Application 17/550,123 is a continuation of application No. 16/940,880, filed on Jul. 28, 2020, granted, now 11,239,847, issued on Jan. 12, 2022.
Application 16/940,880 is a continuation of application No. 16/167,440, filed on Oct. 22, 2018, granted, now 10,727,841.
Prior Publication US 2024/0267051 A1, Aug. 8, 2024
Int. Cl. H03L 7/087 (2006.01); H03L 7/099 (2006.01)
CPC H03L 7/087 (2013.01) [H03L 7/099 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A circuit comprising:
a phase frequency detector (PFD) having a first input configured to receive a first clock signal, a second input, and an output;
an oscillator having an input coupled to the output of the PFD, and an output coupled to the second input of the PFD;
a detector circuit comprising a first clock input coupled to the output of the oscillator, a first output, and a second output;
a clock generator circuit having an input coupled to the first output of the detector circuit, and an output; and
a selector circuit having a first input coupled to the output of the oscillator, a second input coupled to the output of the clock generator circuit, and a selection input coupled to the second output of the detector circuit.