US 12,476,639 B2
Chained command architecture for packet processing
Sreedhar Ravipalli, Cupertino, CA (US); Jing Miao, Livermore, CA (US); Raghucharan Boddupalli, Bangalore (IN); Luan Bui, San Jose, CA (US); Dinesh Kotti, Saratoga, CA (US); and Ranjini Rajeevan, Fremont, CA (US)
Assigned to Altera Corporation, San Jose, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jul. 1, 2022, as Appl. No. 17/855,970.
Prior Publication US 2022/0337249 A1, Oct. 20, 2022
Int. Cl. H03K 19/17736 (2020.01); H03K 19/17704 (2020.01)
CPC H03K 19/17744 (2013.01) [H03K 19/17708 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A programmable logic device comprising:
a first portion of programmable elements configured to implement a user logic; and
a second portion of the programmable elements configured to implement an infrastructure processing unit (IPU) to enable the first portion of programmable elements to interface with a plurality of accelerator engines, wherein the IPU is to receive a chained command to cause two or more accelerator engines of the plurality of accelerator engines to perform sequential operations on a data packet in response to the chained command.