US 12,476,638 B2
FPGA-based adjustable clock for audio devices
Eugen Warkentin, Elgin, IL (US); and Mack Mansouri, Wheeling, IL (US)
Assigned to Shure Acquisition Holdings, Inc., Niles, IL (US)
Filed by Shure Acquisition Holdings, Inc., Niles, IL (US)
Filed on Sep. 8, 2023, as Appl. No. 18/243,920.
Prior Publication US 2025/0088191 A1, Mar. 13, 2025
Int. Cl. H03K 19/17736 (2020.01); G06F 1/06 (2006.01)
CPC H03K 19/1774 (2013.01) [G06F 1/06 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An adjustable clock comprising:
a field-programmable gate array (FPGA) comprising:
a numerically-controlled frequency divider configured to:
receive, for each of a plurality of pulses of a reference clock signal, a feedback parameter; and
for each of the plurality of pulses of the reference clock signal, generate, based on the respective feedback parameter, a pulse of a divided clock signal and an indication of a phase error for the pulse of the divided clock signal;
a multi-tap delay line configured to impart a selectable amount of delay on the divided clock signal;
logic configured to select, for each pulse of the divided clock signal and based on the respective indication of the phase error, the selectable amount of delay of the multi-tap delay line; and
a feedback loop configured to generate, based on an output of the multi-tap delay line and for each of the plurality of pulses of the reference clock signal, the feedback parameter,
wherein the FPGA is configured to output an adjustable clock signal based on the output of the multi-tap delay line.