US 12,476,633 B2
Transistor driver circuit and transistor driving method
Hideaki Majima, Minato Tokyo (JP)
Assigned to Kabushiki Kaisha Toshiba, Kawasaki (JP); and Toshiba Electronic Devices & Storage Corporation, Kawasaki (JP)
Filed by Kabushiki Kaisha Toshiba, Tokyo (JP); and Toshiba Electronic Devices & Storage Corporation, Tokyo (JP)
Filed on Oct. 17, 2023, as Appl. No. 18/488,880.
Claims priority of application No. 2022-166949 (JP), filed on Oct. 18, 2022.
Prior Publication US 2024/0128970 A1, Apr. 18, 2024
Int. Cl. H03K 17/284 (2006.01)
CPC H03K 17/284 (2013.01) 12 Claims
OG exemplary drawing
 
1. A transistor driver circuit comprising:
a driving force limitation circuit configured to maintain a gate potential of a transistor to be driven at a driving force limitation potential when the transistor to be driven is driven, the driving force limitation potential corresponding to a threshold voltage of the transistor to be driven; and
a delay-time adjustment circuit configured to cause the gate potential to transition to the driving force limitation potential when the driving force limitation circuit is in operation,
wherein the driving force limitation circuit includes a driving-force variable, first MOS transistor, and a driving-force constant, second MOS transistor connected in series with the first MOS transistor.