| CPC H03K 5/1252 (2013.01) [G06F 1/08 (2013.01)] | 16 Claims |

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1. A skew-tolerant, glitch-free multiplexer circuit comprising:
a first flip-flop configured to receive a gate signal and to generate an output;
auto-burst detection circuitry having second and third flip-flops, the auto-burst detection circuitry configured to receive the output at the second flip-flop and to generate an auto-burst detection circuitry output from the third flip-flop;
a plurality of flip-flops configured to receive the auto-burst detection circuitry output, wherein each of the plurality of flip-flops is configured to provide an input to a multiplexer; and
reset envelope generation circuitry configured to receive the output from the first flip-flop wherein the reset envelope generation circuitry includes at least two flip-flops.
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