US 12,476,623 B2
Electronic circuit
Takeaki Yajima, Tokyo (JP)
Assigned to JAPAN SCIENCE AND TECHNOLOGY AGENCY, Kawaguchi (JP)
Filed by JAPAN SCIENCE AND TECHNOLOGY AGENCY, Kawaguchi (JP)
Filed on Jul. 28, 2023, as Appl. No. 18/227,473.
Application 18/227,473 is a division of application No. 17/881,034, filed on Aug. 4, 2022, granted, now 11,757,433.
Application 17/881,034 is a continuation of application No. 17/408,599, filed on Aug. 23, 2021, granted, now 11,444,605, issued on Sep. 13, 2022.
Application 17/408,599 is a continuation of application No. PCT/JP2020/006045, filed on Feb. 17, 2020.
Claims priority of application No. 2019-036951 (JP), filed on Feb. 28, 2019.
Prior Publication US 2023/0387891 A1, Nov. 30, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H03K 3/02 (2006.01); H03K 5/01 (2006.01); H03K 19/20 (2006.01); H03K 5/00 (2006.01)
CPC H03K 3/02 (2013.01) [H03K 5/01 (2013.01); H03K 19/20 (2013.01); H03K 2005/00013 (2013.01)] 16 Claims
OG exemplary drawing
 
1. An electronic circuit comprising:
a spike generation circuit that outputs an isolated spike signal to an output terminal and reset an internal state of the spike generation circuit to an initial value when the internal state reaches a threshold value, wherein the internal state depends on a history of an input current input to an input terminal;
a wireless communication circuit that receives the isolated spike signal output from the spike generation circuit and outputs electromagnetic waves to an antenna; and
a memory circuit that has a first input terminal and a first output terminal, and maintains a level of the first output terminal at one of a high level and a low level when the one of the high level and the low level is input to the first input terminal, the first output terminal being coupled to the input terminal of the spike generation circuit.