US 12,476,622 B2
Duty cycle calibration circuit, corresponding transmitter, communication system and method
Massimo Pozzoni, Pavia (IT); Paolo Viola, Pavia (IT); Pasquale D'Argenio, Mercogliano (IT); and Augusto Andrea Rossi, Pavia (IT)
Assigned to STMicroelectronics International N.V., Geneva (CH)
Filed by STMicroelectronics International N.V., Geneva (CH)
Filed on Apr. 10, 2024, as Appl. No. 18/631,798.
Claims priority of application No. 102023000007998 (IT), filed on Apr. 24, 2023.
Prior Publication US 2024/0356537 A1, Oct. 24, 2024
Int. Cl. H03K 3/017 (2006.01); H03K 5/24 (2006.01); H03K 17/567 (2006.01)
CPC H03K 3/017 (2013.01) [H03K 5/24 (2013.01); H03K 17/567 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A circuit, comprising:
a clock signal generator configured to produce a clock signal, the clock signal generator having a duty cycle control input to control a duty cycle of the clock signal;
a multiplexer having inputs configured to multiplex input data patterns into a multiplexed output pattern in response to rising and falling edges of the clock signal;
a calibration data pattern generator configured to generate a first calibration data pattern and a second calibration data pattern as input data patterns to the multiplexer, wherein the first calibration data pattern has a first configuration of transitions between logical values, wherein the second calibration data pattern is a replica of the first calibration data pattern, wherein the second calibration data pattern has a second configuration of transitions between logical values, wherein the second configuration of transitions between logical values is shifted with respect to the first configuration of transitions; and
a control circuitry configured to generate a duty cycle control signal for the duty cycle control input of the clock signal generator, the control circuitry comprising:
an averaging circuitry coupled to an output of the multiplexer, the averaging circuitry configured to produce a first averaged signal and a second averaged signal in response to the multiplexer receiving the first calibration data pattern and the second calibration data pattern, respectively, and
a duty cycle control circuitry configured to:
detect a duty cycle distortion condition in the clock signal in response to the first averaged signal and the second averaged signal failing to have the same value; and
apply a duty cycle distortion compensation signal to the duty cycle control input based on an amount the first averaged signal and the second averaged signal diverge from the same value while targeting a 50% duty cycle of the clock signal of the clock signal generator.