US 12,476,619 B2
Signal driver circuit, and a semiconductor apparatus using the same
Hyun Su Park, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Feb. 1, 2024, as Appl. No. 18/429,768.
Claims priority of application No. 10-2023-0119146 (KR), filed on Sep. 7, 2023.
Prior Publication US 2025/0088176 A1, Mar. 13, 2025
Int. Cl. H03K 19/01 (2006.01); H03K 3/011 (2006.01); H03K 3/037 (2006.01); H03K 19/20 (2006.01); H03K 5/00 (2006.01); H03K 5/01 (2006.01)
CPC H03K 3/011 (2013.01) [H03K 3/037 (2013.01); H03K 19/20 (2013.01); H03K 2005/00013 (2013.01); H03K 5/01 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A signal driver circuit comprising:
a pre-driving circuit configured to generate a first pre-driving signal and a second pre-driving signal based on an input signal and a clock signal;
a driving signal generating circuit configured to generate a pull-up driving signal based on the first pre-driving signal and a complementary delayed output signal and configured to generate a pull-down driving signal based on the second pre-driving signal and the complementary delayed output signal;
a main driving circuit configured to generate an output signal based on the pull-up driving signal and the pull-down driving signal; and
an output control circuit configured to latch the output signal and configured to delay the output signal to generate a delayed output signal and the complementary delayed output signal.