US 12,476,599 B2
Temperature tolerant input stages for circuits
Satoshi Sakurai, San Carlos, CA (US)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Apr. 28, 2022, as Appl. No. 17/731,730.
Prior Publication US 2023/0353107 A1, Nov. 2, 2023
Int. Cl. H03F 3/45 (2006.01); H03K 3/0233 (2006.01)
CPC H03F 3/45273 (2013.01) [H03K 3/0233 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A circuit comprising:
a high-side input stage including differential signal inputs configured to receive first and second signals respectively of a differential input signal; and
a low-side input stage comprising:
first and second differential input transistors each having a control terminal;
a first PMOS transistor having a gate configured to receive the first signal of the differential input signal, the first PMOS transistor having a source coupled to the control terminal of the first differential input transistor;
a second PMOS transistor having a gate configured to receive the second signal of the differential input signal, the second PMOS transistor having a source coupled to the control terminal of the second differential input transistor; and
a current mirror coupled to the sources of the first and second PMOS transistors.