US 12,476,355 B2
System
Harshitha Thippur Shivamurthy, Eindhoven (NL); Rabia Syeda, Eindhoven (NL); Rocío Gabriela Molina Moreno, Eindhoven (NL); Cristine Aguila Badiao, Eindhoven (NL); Pieter Lok, Leur (NL); Adrianus Buijsman, Nijmegen (NL); Leo van Gemert, Nijmegen (NL); Maarten Lont, Eindhoven (NL); Giorgio Carluccio, Eindhoven (NL); and Antonius Johannes Matheus de Graauw, Haelen (NL)
Assigned to NXP B.V., Eindhoven (NL)
Filed by NXP B.V., Eindhoven (NL)
Filed on Oct. 30, 2023, as Appl. No. 18/496,975.
Claims priority of application No. 22205603 (EP), filed on Nov. 4, 2022.
Prior Publication US 2024/0154300 A1, May 9, 2024
Int. Cl. H01Q 1/38 (2006.01); H01Q 1/22 (2006.01); H01Q 21/24 (2006.01); H01Q 21/29 (2006.01)
CPC H01Q 1/38 (2013.01) [H01Q 1/2283 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A system comprising:
a waveguide assembly comprising a plurality of waveguides, the plurality of waveguides comprising at least a first waveguide and a second waveguide, and
an integrated circuit package, IC package, comprising a plurality of launchers to one or more of transmit signalling to and receive signalling from a respective one of the plurality of waveguides,
wherein the waveguide assembly comprises a surface configured to be located adjacent the IC package and wherein each of the plurality of waveguides comprise an opening in the surface configured to be aligned with its respective launcher,
wherein each of the openings has a major dimension and a minor dimension, wherein the major dimension is larger than the minor dimension,
wherein the major dimension of at least the opening of the first waveguide is oriented perpendicular to the major dimension of the opening of the second waveguide,
wherein each of the launchers comprises a differential patch launcher comprising a planar body having a slot therein extending from an outer edge along a line of symmetry of the planar body,
wherein a differential microstrip line comprising a first line and a second line is coupled to the planar body at opposite sides of the slot, and
wherein at least one of the first line or the second line of the microstrip line comprises a compensation component configured to provide for common mode reduction.