US 12,476,235 B2
Multi-chip packaging
Robert L. Sankman, Phoenix, AZ (US); Sairam Agraharam, Chandler, AZ (US); Shengquan Ou, Chandler, AZ (US); Thomas J De Bonis, Tempe, AZ (US); Todd Spencer, Chandler, AZ (US); Yang Sun, Chandler, AZ (US); and Guotao Wang, Chandler, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 27, 2023, as Appl. No. 18/397,891.
Application 18/397,891 is a continuation of application No. 17/716,934, filed on Apr. 8, 2022, granted, now 12,199,085.
Application 17/716,934 is a continuation of application No. 17/587,657, filed on Jan. 28, 2022, granted, now 11,817,444, issued on Nov. 14, 2023.
Application 17/587,657 is a continuation of application No. 16/892,698, filed on Jun. 4, 2020, granted, now 11,348,911, issued on May 31, 2022.
Application 16/892,698 is a continuation of application No. 15/996,870, filed on Jun. 4, 2018, granted, now 10,700,051, issued on Jun. 30, 2020.
Prior Publication US 2024/0128256 A1, Apr. 18, 2024
Int. Cl. H01L 25/00 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/538 (2006.01); H01L 25/18 (2023.01)
CPC H01L 25/50 (2013.01) [H01L 21/563 (2013.01); H01L 23/5381 (2013.01); H01L 23/5385 (2013.01); H01L 24/06 (2013.01); H01L 24/11 (2013.01); H01L 24/16 (2013.01); H01L 24/17 (2013.01); H01L 25/18 (2013.01); H01L 2224/0603 (2013.01); H01L 2224/11013 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16238 (2013.01); H01L 2224/1703 (2013.01); H01L 2224/17051 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A multi-chip package, comprising:
a first bridge interconnect and a second bridge interconnect in a molding material, the second bridge interconnect laterally spaced apart from the first bridge interconnect, the first bridge interconnect comprising a first plurality of bridge contacts and a second plurality of bridge contacts, and the second bridge interconnect comprising a third plurality of bridge contacts and a fourth plurality of bridge contacts;
a first plurality of die vias in the molding material, the first plurality of die vias laterally adjacent to a first side of the first bridge interconnect;
a second plurality of die vias in the molding material, the second plurality of die vias laterally between a second side of the first bridge interconnect and a first side of the second bridge interconnect;
a third plurality of die vias in the molding material, the third plurality of die vias laterally adjacent to a second side of the second bridge interconnect;
a first die electrically coupled to the first plurality of bridge contacts, and the first die electrically coupled to the first plurality of die vias;
a second die electrically coupled to the second plurality of bridge contacts, the second die electrically coupled to the second plurality of die vias, and the second die electrically coupled to the third plurality of bridge contacts;
a third die electrically coupled to the fourth plurality of bridge contacts, and the third die electrically coupled to the third plurality of die vias;
a substrate beneath the first bridge interconnect, the second bridge interconnect, the first plurality of die vias, the second plurality of die vias and the third plurality of die vias, the substrate electrically coupled to the first plurality of die vias, the second plurality of die vias and the third plurality of die vias; and
an underfill material along sides and along a bottom of the molding material, the underfill material between the substrate and the molding material, and the underfill material in contact with the bottom of the molding material.