US 12,476,214 B2
Solder interconnect hierarchy for heterogeneous electronic device packaging
Yue Deng, Chandler, AZ (US); Jung Kyu Han, Chandler, AZ (US); Liang He, Chandler, AZ (US); Gang Duan, Chandler, AZ (US); and Rahul N. Manepalli, Chandler, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 21, 2021, as Appl. No. 17/558,297.
Prior Publication US 2023/0197660 A1, Jun. 22, 2023
Int. Cl. H01L 23/00 (2006.01); H01L 23/498 (2006.01)
CPC H01L 24/16 (2013.01) [H01L 23/49811 (2013.01); H01L 24/13 (2013.01); H01L 2224/13109 (2013.01); H01L 2224/13111 (2013.01); H01L 2224/16225 (2013.01); H01L 2924/014 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
an integrated circuit (IC) die having first interconnections electrically coupled to a first end of contact pillars with first solder bumps; and
second interconnections electrically coupled to a second end of the contact pillars with second solder bumps;
wherein the first solder bumps are to be combined with third solder bumps with a first soldering technique to form first solder joints and the second solder bumps are to be combined with fourth solder bumps with a second soldering technique to form second solder joints having a lower melting temperature than the first solder joints.