US 12,476,200 B2
Semiconductor structure and manufacturing method of semiconductor structure
Zhiyuan Lu, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Jan. 30, 2023, as Appl. No. 18/161,126.
Claims priority of application No. 202210938684.4 (CN), filed on Aug. 5, 2022.
Prior Publication US 2024/0047371 A1, Feb. 8, 2024
Int. Cl. H01L 21/311 (2006.01); H01L 23/544 (2006.01)
CPC H01L 23/544 (2013.01) [H01L 21/31144 (2013.01); H01L 2223/54426 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A manufacturing method of a semiconductor structure, comprising:
providing a substrate comprising an array area and a peripheral area, wherein the peripheral area comprises a mark area and a blank area adjoining the mark area;
forming, on the substrate, a target layer and a first core layer disposed on the target layer, the first core layer comprising a first array core layer disposed on the array area, a first mark core layer disposed on the mark area and a first cap layer disposed on the blank area, where the first cap layer has an inclined sidewall, and a top dimension of the first cap layer is smaller than a bottom dimension of the first cap layer;
forming a first dielectric layer covering a sidewall of the first core layer;
forming a first filling layer that covers a surface of the first dielectric layer and fills a gap in the first core layer; and
etching the first dielectric layer and the target layer along a sidewall of the first array core layer and a sidewall of the first mark core layer to transfer a pattern of the first core layer and a pattern of the first filling layer to the target layer.