US 12,476,183 B2
Punch-through interconnect feature to couple upper electrodes of capacitors of multi-level memory arrays
Travis W. Lajoie, Forest Grove, OR (US); Juan Alzate Vinasco, Tigard, OR (US); Abhishek Anil Sharma, Portland, OR (US); Van H. Le, Beaverton, OR (US); Moshe Dolejsi, Portland, OR (US); Yu-Wen Huang, Beaverton, OR (US); Kimberly Pierce, Beaverton, OR (US); Jared Stoeger, Portland, OR (US); and Shem Ogadhoh, West Linn, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Mar. 11, 2022, as Appl. No. 17/692,350.
Prior Publication US 2023/0290722 A1, Sep. 14, 2023
Int. Cl. H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H10B 12/00 (2023.01)
CPC H01L 23/5226 (2013.01) [H01L 23/5283 (2013.01); H01L 23/53223 (2013.01); H01L 23/53238 (2013.01); H01L 23/53266 (2013.01); H10B 12/0335 (2023.02); H10B 12/315 (2023.02)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
a first memory cell including (i) a first transistor and (ii) a first capacitor coupled to the first transistor, and where an upper electrode of the first capacitor is coupled to a first conductive structure;
a second memory cell above the first memory cell, the second memory cell including (i) a second transistor and (ii) a second capacitor coupled to the second transistor, and where an upper electrode of the second capacitor is coupled to a second conductive structure; and
an interconnect feature being a continuous and monolithic body of conductive material, the continuous and monolithic body extending through the second conductive structure, and further extending through the first conductive structure.