US 12,476,176 B2
Glass core substrate printed circuit board for warpage reduction
Carlton Hanna, San Jose, CA (US); Georg Seidemann, Landshut (DE); Eduardo De Mesa, Munich (DE); Abdallah Bacha, Munich (DE); and Lizabeth Keser, San Diego, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Mar. 29, 2022, as Appl. No. 17/707,183.
Prior Publication US 2023/0317582 A1, Oct. 5, 2023
Int. Cl. H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01L 23/14 (2006.01); H01L 23/48 (2006.01); H01L 25/065 (2023.01); H01L 23/00 (2006.01); H01L 23/538 (2006.01)
CPC H01L 23/49822 (2013.01) [H01L 21/4857 (2013.01); H01L 21/486 (2013.01); H01L 23/145 (2013.01); H01L 23/481 (2013.01); H01L 23/49816 (2013.01); H01L 23/49838 (2013.01); H01L 25/0655 (2013.01); H01L 23/5381 (2013.01); H01L 23/5383 (2013.01); H01L 23/5386 (2013.01); H01L 24/16 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16237 (2013.01); H01L 2924/3511 (2013.01)] 25 Claims
OG exemplary drawing
 
1. An electronic device, comprising:
a redistribution layer (RDL) comprising one or more sublayers of conductive traces in an organic material;
a stiffening layer comprising a first surface contacting a first surface of the RDL and comprising a through layer via (TLV), wherein the stiffening layer is a multi-layer stack comprising at least one glass layer and at least one ceramic layer; and
multiple integrated circuits (ICs) on a second surface of the RDL, wherein the conductive traces of the RDL provide electrical continuity between at least one of the multiple ICs and the TLV of the stiffening layer.