US 12,476,163 B2
Semiconductor device and semiconductor module
Takahiro Nakano, Kariya (JP); Seigo Oosawa, Kariya (JP); Yasushi Ookura, Kariya (JP); Naohito Mizuno, Kariya (JP); and Yoshihiro Inutsuka, Kariya (JP)
Assigned to DENSO CORPORATION, Kariya (JP)
Filed by DENSO CORPORATION, Kariya (JP)
Filed on Oct. 12, 2022, as Appl. No. 17/964,381.
Application 17/964,381 is a continuation of application No. PCT/JP2021/011411, filed on Mar. 19, 2021.
Claims priority of application No. 2020-074422 (JP), filed on Apr. 17, 2020; and application No. 2021-028963 (JP), filed on Feb. 25, 2021.
Prior Publication US 2023/0032353 A1, Feb. 2, 2023
Int. Cl. H01L 23/367 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 21/683 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/538 (2006.01)
CPC H01L 23/367 (2013.01) [H01L 21/4853 (2013.01); H01L 21/4871 (2013.01); H01L 21/565 (2013.01); H01L 21/568 (2013.01); H01L 21/6835 (2013.01); H01L 23/3121 (2013.01); H01L 23/5386 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 2221/68372 (2013.01); H01L 2224/214 (2013.01)] 4 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a semiconductor element having a front surface, a rear surface positioned opposite the front surface, and a side surface connecting the front surface and the rear surface;
a conductive member having an upper surface that is joined to the rear surface of the semiconductor element and a lower surface that is opposite the upper surface;
a sealing member covering the side surface of the semiconductor element and a part of the conductive member; and
a rewiring layer including an insulating layer, a first electrode, a second electrode, a first externally-exposed layer, and second externally-exposed layer,
the insulating layer covering the front surface of the semiconductor element and a part of the sealing member,
the first electrode and the second electrode being connected to the semiconductor element,
the first externally-exposed layer being conductive and covering a portion of the first electrode that is exposed from the insulating layer,
the second externally-exposed layer being conductive and covering a portion of the second electrode that is exposed from the insulating layer, wherein
an end of the second electrode that is positioned opposite the semiconductor element is extended to a portion of the rewiring layer that is positioned outside an outline of the semiconductor element,
the second externally-exposed layer covers a portion of the second electrode that is positioned outside the outline of the semiconductor element,
the rear surface of the semiconductor element is entirely positioned inside an outline of the conductive member,
a plane size of the conductive member along the rear surface of the semiconductor element is larger than the rear surface of the semiconductor element,
the conductive member is formed of a metal sintered body,
the lower surface of the conductive member is exposed from the sealing member,
the conductive member includes a projecting portion that is positioned outside the outline of the semiconductor element,
the projecting portion has a plurality of voids of micrometer order or less, the plurality of voids extends at least to an outermost surface of the projecting portion, and
the projecting portion has a lower density than a remaining portion of the conductive member other than the projecting portion.