US 12,475,969 B2
Dynamic random access memory (DRAM) device with variable burst lengths
Thomas Vogelsang, Mountain View, CA (US)
Assigned to Rambus Inc., San Jose, CA (US)
Filed by Rambus Inc., San Jose, CA (US)
Filed on Sep. 12, 2023, as Appl. No. 18/367,381.
Claims priority of provisional application 63/406,593, filed on Sep. 14, 2022.
Prior Publication US 2024/0177794 A1, May 30, 2024
Int. Cl. G11C 11/4093 (2006.01); G11C 11/408 (2006.01); G11C 29/52 (2006.01)
CPC G11C 29/52 (2013.01) [G11C 11/4087 (2013.01); G11C 11/4093 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A dynamic random access memory (DRAM) device comprising:
a first mode of operation having a first burst length and a first column address range;
a second mode of operation having a second burst length and a second column address range, wherein only one of the first burst length and the second burst length is a power of two; and
an error correction code (ECC) block to generate, receive, and store ECC parity associated with data in the first mode of operation and the second mode of operation, wherein a first product of the first column address range and the first burst length and a second product of the second column address range and the second burst length are substantially the same.