US 12,475,967 B2
Semiconductor devices for controlling refresh operations considering repair operations
Sang Hyun Ku, Icheon-si (KR); and Don Hyun Choi, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Dec. 27, 2022, as Appl. No. 18/089,261.
Claims priority of application No. 10-2022-0112434 (KR), filed on Sep. 5, 2022.
Prior Publication US 2024/0079078 A1, Mar. 7, 2024
Int. Cl. G11C 29/44 (2006.01); G11C 29/00 (2006.01); G11C 29/12 (2006.01)
CPC G11C 29/4401 (2013.01) [G11C 29/785 (2013.01); G11C 2029/1202 (2013.01)] 26 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a redundancy control signal generation circuit configured to generate a redundancy control signal by determining whether a row address for an active operation has been repaired through a soft post package repair operation and determining whether a row hammer phenomenon has occurred with respect to the row address;
a first selection address generation circuit configured to generate a first selection address for driving a sub word line or a redundancy word line from one of a repair address and a first internal address, based on the redundancy control signal, wherein the first selection address generation circuit comprises a first selector, and the first selector is configured to receive the repair address, the first internal address, and the redundancy control signal and is configured to output one of the repair address and the first internal address as the first selection address based on a logic level of the redundancy control signal;
a second selection address generation circuit configured to generate a second selection address for driving the sub word line or the redundancy word line from one of a fixed address and a second internal address, based on the redundancy control signal, wherein the second selection address generation circuit comprises a fixed address storage circuit and a second selector, wherein the fixed address storage circuit is configured to store and output the fixed address, and wherein the second selector is configured to receive the fixed address, the second internal address, and the redundancy control signal and is configured to output one of the fixed address and the second internal address as the second selection address based on the logic level of the redundancy control signal; and
a memory bank configured to include a normal region and a redundancy region,
wherein the redundancy region includes a soft redundancy word line driven for the soft post package repair operation, and a hard redundancy word line driven for a hard post package repair operation.