US 12,475,950 B2
Adaptive bias decoder for non-volatile memory system
Hieu Van Tran, San Jose, CA (US); Thuan Vu, San Jose, CA (US); Stanley Hong, San Jose, CA (US); Stephen Trinh, San Jose, CA (US); Anh Ly, San Jose, CA (US); Nhan Do, Saratoga, CA (US); and Mark Reiten, Alamo, CA (US)
Assigned to Silicon Storage Technology, Inc., San Jose, CA (US)
Filed by Silicon Storage Technology, Inc., San Jose, CA (US)
Filed on Dec. 11, 2023, as Appl. No. 18/536,123.
Application 18/536,123 is a division of application No. 17/140,924, filed on Jan. 4, 2021, granted, now 11,875,852.
Claims priority of provisional application 63/048,470, filed on Jul. 6, 2020.
Prior Publication US 2024/0105263 A1, Mar. 28, 2024
Int. Cl. G11C 7/12 (2006.01); G11C 11/54 (2006.01); G11C 16/08 (2006.01); G11C 16/24 (2006.01)
CPC G11C 16/08 (2013.01) [G11C 11/54 (2013.01); G11C 16/24 (2013.01); G11C 2216/04 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A non-volatile memory system, comprising:
an array of non-volatile memory cells arranged in rows and columns, each non-volatile memory cell comprising a source and a drain;
a plurality of bit lines, each of the plurality of bit lines coupled to the drain of each non-volatile memory cell in a column of non-volatile memory cells;
a source line coupled to the source of each non-volatile memory cell; and
an adaptive bias decoder coupled to the source line and a word line of the array to generate a voltage and apply the voltage to the word line during an operation, wherein the adaptive bias decoder comprises an adjustable resistor comprising a first end and a second end, the first end coupled to an adjustable current source to provide the voltage and the second end coupled to the source line, wherein the adaptive bias decoder adjusts a resistance of the adjustable resistor to thereby adjust the voltage in response to changes in a voltage of the source line.