US 12,475,939 B2
Pre-decoder circuitry
Jin Seung Son, McKinney, TX (US); and Mingdong Cui, Folsom, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on May 17, 2024, as Appl. No. 18/667,802.
Application 18/667,802 is a continuation of application No. 17/831,332, filed on Jun. 2, 2022, granted, now 11,990,176.
Prior Publication US 2024/0304233 A1, Sep. 12, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 13/00 (2006.01); G11C 11/4074 (2006.01); G11C 11/408 (2006.01); G11C 11/4093 (2006.01); G11C 11/4096 (2006.01)
CPC G11C 11/4087 (2013.01) [G11C 11/4074 (2013.01); G11C 11/4093 (2013.01); G11C 11/4096 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A method of operating memory, comprising:
providing a first input decoding address signal to a gate of a first transistor of first pre-decoder circuitry and a second input decoding address signal to a gate of a second transistor of the first pre-decoder circuitry;
providing a third input decoding address signal and a fourth input decoding address signal to a NOR logic gate of second pre-decoder circuitry; and
providing a de-selection bias condition for a first gate of a first n-type transistor of decoder circuitry and a second gate of a second n-type transistor of the decoder circuitry based on voltage values of the first, second, third, and fourth input decoding address signals.