US 12,475,938 B2
Delay control circuit and method, and semiconductor memory
Zequn Huang, Hefei (CN); and Kai Sun, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Aug. 9, 2023, as Appl. No. 18/446,508.
Application 18/446,508 is a continuation of application No. PCT/CN2022/127123, filed on Oct. 24, 2022.
Claims priority of application No. 202211223514.4 (CN), filed on Oct. 8, 2022.
Prior Publication US 2024/0127881 A1, Apr. 18, 2024
Int. Cl. G11C 11/40 (2006.01); G06F 1/08 (2006.01); G06F 11/10 (2006.01); G11C 11/4076 (2006.01); H03K 5/133 (2014.01); H03K 5/00 (2006.01)
CPC G11C 11/4076 (2013.01) [G06F 1/08 (2013.01); G06F 11/106 (2013.01); H03K 5/133 (2013.01); H03K 2005/00058 (2013.01); H03K 2005/00241 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A delay control circuit, comprising
a clock circuit and a delay circuit, wherein
the clock circuit is configured to receive a temperature adjustment signal, and generate a first clock signal according to the temperature adjustment signal, wherein a clock cycle of the first clock signal is a preset value; and
the delay circuit is configured to receive the first clock signal and an initial command signal, and perform delay processing on the initial command signal according to the first clock signal, so as to obtain a target command signal, wherein a time interval between the target command signal and the initial command signal meets a preset timing condition; the clock circuit comprises an oscillator circuit and a fuse circuit, the fuse circuit is configured to provide a fuse signal for the oscillator circuit, wherein a target mode value indicated by the fuse signal is determined under a test mode; and
the oscillator circuit is further configured to generate the first clock signal according to the fuse signal and the temperature adjustment signal; the clock circuit further comprises a selection circuit;
the fuse circuit is further configured to set a value of a second test mode signal to be a first candidate mode value under the test mode, and send the second test mode signal to the oscillator circuit;
the oscillator circuit is further configured to generate a test clock signal according to the second test mode signal; and
the selection circuit is configured to receive a first test mode signal, and select the test clock signal for output according to the first test mode signal.