US 12,475,856 B2
Gate driver and display device including the same
Nahyeon Cha, Yongin-si (KR); Kyungho Kim, Yongin-si (KR); and Sang Yong No, Yongin-si (KR)
Assigned to Samsung Display Co., Ltd., Yongin-si (KR)
Filed by Samsung Display Co., LTD., Yongin-si (KR)
Filed on Dec. 12, 2024, as Appl. No. 18/978,445.
Claims priority of application No. 10-2024-0007508 (KR), filed on Jan. 17, 2024.
Prior Publication US 2025/0232731 A1, Jul. 17, 2025
Int. Cl. G09G 3/3266 (2016.01); G09G 3/32 (2016.01); G09G 3/3233 (2016.01)
CPC G09G 3/3266 (2013.01) [G09G 3/32 (2013.01); G09G 3/3233 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0852 (2013.01); G09G 2300/0861 (2013.01); G09G 2310/08 (2013.01); G09G 2320/045 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A gate driver, comprising:
first to nth (n is a natural number greater than 2) stages, a kth (k is a natural number greater than 1 and less than n) stage among the first to nth stages including:
a first transistor including a gate which receives a clock signal, a first terminal which receives an input signal, and a second terminal electrically connected to a first control node;
a fifth transistor including a gate electrically connected to an inverting control node, a first terminal which receives a high gate voltage, and a second terminal electrically connected to an output node outputting a gate signal;
a sixth transistor including a gate electrically connected to a second control node, a first terminal which receives a low gate voltage, and a second terminal electrically connected to the output node;
a fourth transistor including a gate which receives the low gate voltage, a first terminal electrically connected to the first control node, a second terminal electrically connected to the second control node, and a back gate; and
a seventh transistor including a gate which receives a voltage of the inverting control node of a k+1th stage, a first terminal which receives a voltage of the first control node or the second control node of a k−1th stage, and a second terminal electrically connected to the back gate of the fourth transistor.