US 12,475,839 B2
Pixel driving circuit and driving method therefor, and display panel
Minghua Xuan, Beijing (CN); Dongni Liu, Beijing (CN); Qi Qi, Beijing (CN); Jing Liu, Beijing (CN); and Han Yue, Beijing (CN)
Assigned to BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Filed by BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Filed on Jul. 30, 2024, as Appl. No. 18/788,139.
Application 18/788,139 is a continuation of application No. 18/469,557, filed on Sep. 19, 2023, granted, now 12,080,229.
Application 18/469,557 is a continuation of application No. 17/426,594, granted, now 11,804,169, issued on Oct. 31, 2023, previously published as PCT/CN2020/137141, filed on Dec. 17, 2020.
Claims priority of application No. 202010003826.9 (CN), filed on Jan. 3, 2020.
Prior Publication US 2024/0386842 A1, Nov. 21, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G09G 3/32 (2016.01); G09G 3/3208 (2016.01); G09G 3/3233 (2016.01); G09G 3/3266 (2016.01); G11C 19/28 (2006.01)
CPC G09G 3/32 (2013.01) [G09G 3/3208 (2013.01); G09G 3/3233 (2013.01); G09G 3/3266 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/0809 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0842 (2013.01); G09G 2300/0861 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/061 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0233 (2013.01); G09G 2330/021 (2013.01); G11C 19/28 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A pixel driving circuit, comprising:
a driving control sub-circuit including:
a first driving sub-circuit including a driving transistor and a first capacitor, wherein a first electrode of the first capacitor is connected to a first power supply voltage signal terminal, a second electrode of the first capacitor is connected to a first node, and a gate of the driving transistor is connected to the first node;
a first data writing sub-circuit connected to a first scanning signal terminal, a first data signal terminal, and a first electrode of the driving transistor, wherein the first data writing sub-circuit is configured to write a first data signal from the first data signal terminal into the first electrode of the driving transistor in response to a first scanning signal received from the first scanning signal terminal; and
a first control sub-circuit connected to an enable signal terminal, the first power supply voltage signal terminal, the driving transistor, and a first electrode of an element to be driven, wherein the first control sub-circuit is configured to, in response to an enable signal received from the enable signal terminal, make the first power supply voltage signal terminal be electrically connected with the first electrode of the driving transistor, and make a second electrode of the driving transistor be electrically connected with the first electrode of the element to be driven; and
a time control sub-circuit including:
a second driving sub-circuit including a first transistor and a second capacitor, wherein a first electrode of the second capacitor is connected to a second node, a second electrode of the second capacitor is connected to a third node, and a gate of the first transistor is connected to the third node;
a second data writing sub-circuit connected to a second scanning signal terminal, a second voltage signal terminal, a second data signal terminal, the second node, and a first electrode of the first transistor, wherein the second data writing sub-circuit is configured to, in response to a second scanning signal received from the second scanning signal terminal, write a second data signal from the second data signal terminal into the second node, and write a second voltage signal from the second voltage signal terminal into the first electrode of the first transistor; and
a second control sub-circuit connected to the enable signal terminal, a first voltage signal terminal, a third voltage signal terminal, the first driving sub-circuit, the second node and the first transistor, wherein the second control sub-circuit is configured to, in response to the enable signal received from the enable signal terminal, transmit a first voltage signal varying within a set voltage range from the first voltage signal terminal to the second node, and make the first transistor be electrically connected with the third voltage signal terminal and the first driving sub-circuit; wherein
the second driving sub-circuit is configured to output a third voltage signal from the third voltage signal terminal to the first driving sub-circuit at least in response to the second data signal and a change in voltage of the first voltage signal, so as to make the first driving sub-circuit stop outputting a driving signal and control operating duration of the element to be driven.