| CPC G09G 3/2096 (2013.01) [G09G 2310/0286 (2013.01); G09G 2310/0291 (2013.01); G09G 2310/0297 (2013.01); G09G 2330/021 (2013.01)] | 17 Claims |
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1. A driving module, arranged in a display device, wherein the display device comprises a display panel, the display panel comprises a plurality of gate lines arranged in rows, a plurality of data lines arranged in columns and a plurality of pixel circuits arranged in rows and columns arranged in a display region; and the driving module comprises a serial-parallel conversion circuit and a data providing circuit;
the serial-parallel conversion circuit is configured to convert a serial input signal into a parallel output signal and generate a transmission control signal and a common electrode voltage signal in accordance with mode indication information carried by the parallel output signal, and the parallel output signal carries the mode indication information and input display data; and
the data providing circuit is electrically connected to the serial-parallel conversion circuit, and is configured to convert the input display data into output display data and transmit the output display data to a corresponding data line under the control of the transmission control signal;
wherein the serial-parallel conversion circuit comprises a serial-parallel conversion module, a mode conversion module and a common electrode voltage generation module;
the serial-parallel conversion module is configured to convert the serial input signal into the parallel output signal;
the mode conversion module is configured to generate the transmission control signal corresponding to a current display mode in accordance with the mode indication information carried by the parallel output signal, provide the transmission control signal and at least one bit of information in the mode indication information to the data providing circuit, and provide the mode indication information to the common electrode voltage generation module; and
the common electrode voltage generation module is configured to generate a common electrode voltage, a first display control voltage and a second display control voltage corresponding to the current display mode in accordance with the mode indication information;
wherein the serial-parallel conversion module comprises an N-stage shift register, N data latches or delay latches (D latches) and M control multiplexing units; the serial input signal is applied to all input ends of the N D latches; where Nis an integer greater than 1, and M is a positive integer;
a chip selection signal is applied to a first input end of a first stage shift register, a system clock signal is applied to all second input ends of the N-stage shift register, an output end of the first stage shift register is electrically connected to a clock signal input end of a first D latch and a first input end of a second stage shift register, and the first stage shift register is configured to shift the chip selection signal under the control of the system clock signal to obtain a first output clock signal, and provide the first output clock signal to the clock signal input end of the first D latch;
an output end of an a-th stage shift register is electrically connected to a first input end of an m-th control multiplexing unit, a second input end of the m-th control multiplexing unit is electrically connected to an output end of an N-th stage shift register, an output end of the m-th control multiplexing unit is electrically connected to a first input end of an (a+1)-th stage shift register, an m-th data bit control signal is applied to a control end of the m-th control multiplexing unit, the m-th control multiplexing unit is configured to control the output end of the a-th stage shift register or the output end of the N-th stage shift register to be connected to the first input end of the (a+1)-th stage shift register under the control of the m-th data bit control signal; the system clock signal is applied to a second input end of the (a+1)-th stage shift register, an output end of the (a+1)-th stage shift register is electrically connected to a clock signal input end of an (a+1)-th stage D latch, and the (a+1)-th stage shift register is configured to shift the signal output by the output end of the a-th stage shift register under the control of the system clock signal obtain an (a+1)-th output clock signal and provide the (a+1)-th output clock signal to the clock signal input end of the (a+1)-th stage D latch;
a first input end of a b-th stage shift register is electrically connected to an output end of a (b-1)-th stage shift register, the system clock signal is applied to a second input end of the b-th stage shift register, an output end of the b-th stage shift register is electrically connected to a clock signal input end of a b-th stage D latch, and the b-th stage shift register is configured to shift the signal output from the output end of the (b-1)-th stage shift register to obtain a b-th output clock signal and provide the b-th output clock signal to the clock signal input end of the b-th stage D latch;
where a is a positive integer, b is a positive integer greater than 1, and b−1 is not equal to a; m is a positive integer less than or equal to M, and M is a positive integer; and
each D latch is configured to output corresponding data in the serial input signal under the control of the signal applied to the clock signal input end of the D latch.
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