US 12,475,825 B2
Display substrate including shift register and display device
Xiaolin Wang, Beijing (CN); Pengcheng Fu, Beijing (CN); Taeyup Min, Beijing (CN); Zhifu Dong, Beijing (CN); and Hui Guo, Beijing (CN)
Assigned to CHONGQING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., Chongqing (CN); and BEIJING BOE TECHNOLOGY DEVELOPMENT CO., LTD., Beijing (CN)
Filed by CHONGQING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., Chongqing (CN); BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN); and BEIJING BOE TECHNOLOGY DEVELOPMENT CO., LTD., Beijing (CN)
Filed on Apr. 17, 2024, as Appl. No. 18/637,592.
Application 18/637,592 is a continuation of application No. PCT/CN2023/091193, filed on Apr. 27, 2023.
Prior Publication US 2024/0428716 A1, Dec. 26, 2024
Int. Cl. G09G 3/3266 (2016.01); G09G 3/20 (2006.01); G11C 19/28 (2006.01)
CPC G09G 3/20 (2013.01) [G11C 19/28 (2013.01); G09G 2300/0408 (2013.01); G09G 2300/0426 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/0286 (2013.01); G09G 2320/043 (2013.01); G09G 2330/04 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A display substrate, comprising:
a base substrate, wherein a shift register and a clock signal line are on the base substrate;
wherein the shift register comprises: an input circuit, an output circuit, a first control circuit, a second control circuit, a first noise reduction circuit and a second noise reduction circuit;
an output end of the input circuit, a control end of the output circuit and a control end of the second control circuit are connected to a first node, an input end of the input circuit is connected to a first scanning input end, and an input end of the output circuit is connected to the clock signal line;
an output end of the first control circuit, an input end of the second control circuit, a control end of the first noise reduction circuit and a control end of the second noise reduction circuit are connected to a second node, an input end of the first control circuit is configured to be connected with a first voltage signal, and an output end of the first noise reduction circuit and an output end of the second noise reduction circuit are configured to be connected with a second voltage signal;
the input circuit comprises a first transistor and a second transistor, a second electrode of the first transistor is connected with a first electrode of the second transistor, a gate electrode of the first transistor is connected with a gate electrode of the second transistor and serves as a control end of the input circuit, a first electrode of the first transistor serves as the input end of the input circuit, and a second electrode of the second transistor serves as the output end of the input circuit,
the first transistor and the second transistor are both oxide transistors, and the second node is connected to the second voltage signal only through the second control circuit, and a potential of the second node is pulled down only through the second control circuit;
the first control circuit comprises: a seventh transistor, a first electrode of the seventh transistor serves as the input end of the first control circuit, a second electrode of the seventh transistor serves as the output end of the first control circuit, and a gate electrode of the seventh transistor serves as the control end of the first control circuit;
the seventh transistor comprises:
a first semiconductor block, comprising a first end and a second end;
a second semiconductor block, comprising a third end and a fourth end; and
a first floating electrode, overlapped with the first semiconductor block and located between the first end and the second end; and
a second floating electrode, overlapped with the second semiconductor block and located between the third end and the fourth end,
wherein a first electrode of the seventh transistor is connected with the first end and the third end, and a second electrode of the seventh transistor is connected with the second end and the fourth end.